System Overview
Designed and developed a digital bus controller and rudimentary CPU architecture on an FPGA platform. The project provided profound insights into the foundational mechanics of microprocessor clock cycles, data movement, and instruction execution.
Development & Simulation
- Hardware Description & Logic: Authored comprehensive SystemVerilog code to implement a robust Finite State Machine (FSM) tailored for data arbitration.
- Bus Arbitration & Memory Management: Engineered the logic to seamlessly move input values from physical switches across memory modules (RAM/ROM) and peripherals, safely loading data onto buses and registers for calculation without bus contention.
- Verification & Synthesis: Utilized Intel Quartus Prime for synthesis and ModelSim for rigorous testbench simulation, ensuring the processor successfully clocked through instructions to form a functionally proven digital system.