Project Overview
Collaborated within a team environment at the University of Southampton (EEE) to design, simulate, and integrate a Full-Custom Integrated Circuit (IC) utilizing the industry-standard TSMC 65 nm CMOS process node.
Technical Implementation
- Circuit Design & Layout: Leveraged Siemens EDA tools (L-Edit, S-Edit) and Verilog HDL to design fundamental processor components, including an up/down counter, a clock generation circuit, a precision adder, and a pattern recognition block.
- System Integration: Successfully integrated these discrete subcircuits and a UART interface into a cohesive, functional chip architecture.
- Industry Compliance: Conducted rigorous physical verification, ensuring full Design Rule Check (DRC) compliance and Layout Versus Schematic (LVS) matching, confirming the design was fully robust and ready for industrial fabrication and tape-out.